00:00 intro 00:56 z80 04:54 Submitted to TT07 06:52 NMOS 08:22 dynamic memory 10:28 z80 was everything in one chip 12:00 hand layout 14:10 most widely used CPU in the 80s 17:27 Tiny Tapeout compromise 18:56 voltage compatibility 19:58 Fits in 4 TT tiles 21:09 comparison table 22:47 What is Tiny Tapeout 24:28 next steps 26:29 bond pads 28:09 multicore z80 28:59 pricing 29:30 why not use an FPGA? 30:30 what to use for 1.8v core? 31:02 all the classics? 31:53 important to preserve the old chips 32:50 the plan 35:19 how can you help?

* Carsten’s background and interest in analog circuit design * Open-source silicon and its benefits vs. challenges * Analog design tools evolution * Obstacles that hinder wider adoption of open-source silicon tools * Advice on approaching an analog design journey

using X-rays to make 3D images of chips with Tomas Aidukas

Jorge Marín - DC / DC converter design and the IEEE chipathon

A look back at 2022 and what I'm looking forward to in 2023

MPW7: https://zerotoasiccourse.com/post/mpw7_submitted/ MPW2: https://groups.google.com/g/skywater-pdk-announce/c/HelusBBUZ20 Efabless Job: https://www.linkedin.com/jobs/view/3293645910/?refId=BA5W4wSSRYOP%2FlHyVfboBw%3D%3D Correo Libre: https://www.fossi-foundation.org/2022/09/13/ecl54 Interactive GDS viewer: https://mattvenn.github.io/wokwi-verilog-gds-test/viewer/tinytapeout.html Olof's blog: https://www.linkedin.com/posts/olofkindgren_its-time-to-to-thank-uvm-and-say-goodbye-activity-6981904420531777536-iJr4?utm_source=share&utm_medium=member_desktop

https://wiki.f-si.org/index.php/FSiC2022 00:00 Intro 01:04 Charles Papon 05:18 Tristan Gingold 09:10 Staf Verhaegen 11:30 Naohiko Shimizu 16:38 Tim Edwards 20:46 Harald Pretl 21:40 Mirjana Videnovic-Misic

00:00 Intro 03:05 Teo's work on optimising adders 04:35 Proppy's work with Jupyter notebooks 05:32 Open source is the key to innovation 07:51 GF180 08:10 When teaching the design of standard cell libraries, what do students struggle most with? 10:15 What does he think engineers least understand, but should, about standard cells? 12:14 What is your tool flow? 16:00 How many cells do you need in a library? 19:24 Why do we need another cell library for GF180? 20:40 How far are we in terms of opensource tools from commercial tools? 22:20 Liberate 25:20 Does he think automated layout of standard cells will be competitive with hand layout in nanometer processes? 29:21 Are there any circuit families from the past that deserve new attention with Moore's Law slowing down? 33:10 Any theories on why nVidia would make a 7.5T standard cell library? Contact James here: james.stine@okstate.edu or on twitter: https://twitter.com/JamesStineJr

Teo's adders: https://github.com/mattvenn/instrumented_adder MPW6 walkthrough: https://youtu.be/MNuoYz_MM-c https://developers.google.com/silicon Free silicon conference: https://wiki.f-si.org/index.php/FSiC2022 Newsletter: https://www.zerotoasiccourse.com/newsletter/

00:00 intro 00:13 moving pictures 00:29 Proppy put sky130 into google colab notebooks: https://colab.research.google.com/gist/proppy/964fa4b9277c3baf9e731872bbad93e4/zerotoasic_project1_1.ipynb#scrollTo=TGgki8I-wPWa 01:12 Teo's work on optimising adders https://blog.yosyshq.com/p/optimising-adders/ 01:53 MPW6 reminder 02:20 Level up your RTL call https://twitter.com/matthewvenn/status/1514927352010186754 02:46 $100 tapeout 04:26 Chips Alliance event https://chipsspring2022.sched.com/ 04:42 WOSET https://twitter.com/mguthaus/status/1521906129126666243 04:57 ChipFlow's first video: https://www.youtube.com/watch?v=rVsOZE80c-k&t=1s 05:28 Ex-ex-ex-clusive MPW2 news 05:45 Maximo's great photo of MPW1 dies: https://twitter.com/maxiborga/status/1522372084671913985

Interview with Dinesh A - Riscduino
00:00 Intro00:45 about Dinesh02:39 Aim of Riscduino04:50 Aim to be pin compatible and with support of compiler and libraries06:10 Join the project - Dinesh is looking for help with analog, verification & embedded07:30 State of the Analog IP08:30 Tell us about your applications to MPW2, 3, 4 & 513:40 Great docs!14:02 Verification16:00 Timing analysis19:40 What do you think about OpenLane?24:10 Pin positions25:40 Clock domains

MPW1 lives, chip scans, epoxy, Efabless, CLEAR FPGA, Makercast & hackchat

Talking about the minimal fab with Leo Moser. Leo recently won a competition run by minimal fab and had a design fabricated.He's published a few blog posts about it here:
About the Minimal Fab: https://mole99.uber.space/2023/Minimal_Fab/About%20Minimal%20Fab%20and%20the%20ICPS%20PDK.html NAND tutorial: https://mole99.uber.space/2024/NAND_tutorial/Design%20of%20a%20NAND%20gate%20using%20the%20ICPS%20PDK.html

January news update!MPW1 silicon & bringup, MPW4 submitted, MPW5 tapeout

Carlos' twitter space: https://twitter.com/carlosedp/status/1469355189891125255 Silicon compiler: https://www.siliconcompiler.com/ Amaranth: https://github.com/amaranth-lang/amaranth MPW2 rerun: https://efabless.com/projects/585 MPW4 application: https://efabless.com/projects/596 Caravel restructure: https://github.com/efabless/caravel SkullFET: https://twitter.com/UriShaked/status/1472258972505812992 Will's FPGA advent calendar: https://twitter.com/WillFlux/status/1465268154733637633

MPW3 App: SoC https://efabless.com/projects/481 SoC source: https://github.com/ChipFlow/caravel_user_project_mpw3.git Amaranth: https://github.com/amaranth-lang/amaranth

In this interview we talk about Staf's recent tapeout, the flexcell standard cell generator and pdk master - a kind of API for pdks.Staf also gives his opinions on the state of the industry and whether we at an inflection point for open source silicon.

Lots of open source ASIC news from November. Check the youtube description for all the links.
https://youtu.be/goOzeELjjnI

In this interview with Matt Guthaus, we talk about:

• Recap - what is OpenRAM
• Why do we need a memory compiler like OpenRAM?
• 3 phases of OpenRAM development
• What’s changed since FOSSi dialup
• MPW2 tapeout of OpenRAM
• Test modes
• What was hard about MPW2
• DRC issues
• Status of OpenLANE support for OpenRAM
• Future plans for OpenRAM
• Access to resistive RAM, hopefully for MPW4

Tom Spyrou is a long time EDA developer who has worked at large and small companies.

• In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
• He was the original architect of PrimeTime STA algorithm.
• Manager of Cadence Common timing Engine and precursor to Open Access
• Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.

We have just heard the announcement that OpenLANE will become the defacto flow for OpenROAD.

So I felt very lucky that he was willing to spend half an hour talking to us about a wide range of topics including:

• OpenROAD history & context
• What is the aim of OpenROAD
• State of the art in industry vs research
• Training the next generation of EDA developers
• Shortage of EDA developers
• Use of other PDKs besides Sky130
• Value of open source PDKs
• Roadmap and improvements: PPA
• Machine learning additions for OpenROAD
• Cloud scale compute for OpenROAD
• OpenLANE and OpenROAD collaboration announcement
• Future hopes

One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1.

In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.

Will Green: learning FPGAs with graphics and project F

00:00 Introducing Dan Rodrigues 01:15 Dan was on the first shuttle 02:30 Converting an FPGA project to an ASIC 03:17 How long it took to prepare his submission? 05:17 What kind of config changes were required? 07:50 VDP-lite - wishbone peripheral that can generate sprites and put out on VGA: https://github.com/dan-rodrigues/caravel_vdp_lite 08:45 No framebuffer 11:20 How many flip flops were required? 12:37 A look at the GDS 14:10 Framebuffer vs racing the beam 16:28 How does the wishbone part work? How can VDP-lite be controlled? 18:10 Do you have projects planned to run on the hardware 19:06 Sam Littlewood’s PCB: https://github.com/samlittlewood/caravel_carrier 25:44 Diadatp made a PR on VGA clock demo for realtime verilator rendering 26:00 Caravel test structure 27:06 Icestation32: https://github.com/dan-rodrigues/icestation-32 28:31 Recommendations from Dan about how to learn more about retro gaming 30:12 Ultimate Gameboy talk: https://www.youtube.com/watch?v=HyzD8pNlpwI

Follow Ed here: https://twitter.com/EdConwaySky Buy his book: https://www.penguinrandomhouse.com/bo... Sign up to my newsletter here: https://www.zerotoasiccourse.com/news...

00:00 Introducing Thomas Parry 00:36 Project is an amateur satellite transceiver 01:02 Thomas wanted a challenging project 01:17 His background 01:50 Working for SystematIC Design in Delft doing analogue chip design 02:29 Design split into 2 repositories, see links below 03:50 Day to day work with Cadence and MentorGraphics industry standard tools 04:25 Pay money to reduce risk - no one to shout at 05:42 Previous interviews with Diego & Lakshmi 06:04 His design process is similar 06:57 Using Klayout for layout 07:15 Using OpenLANE for a small part of the design 08:35 Still uses Magic for extraction of circuit 08:52 Nice structure in his repository 10:24 Overview of the structure of a transceiver 12:20 Difference of the visual appearance of digital vs analogue layout 12:46 Taking a look at the GDS 13:30 Control signals 13:46 Digital section - fractional N divider for the PLL 14:29 9x9 array charge pump output 15:30 VCO - do they always look like bathroom tiles? 15:55 4 inverting amplifiers arranged in a ring 16:35 Created MOSFETs with the generator in Magic, then exported into Klayout 17:08 8x4 blocks of output drivers 17:40 Compensation filter for the PLL is off-chip 18:50 Characterise bandgap in a thermal chamber 19:30 Bandgap references replicated 3 times for different measurement options 20:15 Lovely routing! 21:08 Drawn by hand… 21:14 Ruby & Python scripting for Klayout 21:45 Efabless are working to integrate Klayout more tightly into OpenLANE 22:54 Terminology corner: Corner! 24:04 Typical Typical 25:26 How to get the RF signals in and out of Caravel padring? 26:35 WLCSP 27:20 Currently IO cells are digital 27:44 First 8 pins can be switched to analogue, but not ideal for high frequency 28:16 Power amplification 28:58 What are the next steps? Complete the TX chain 30:20 How to get started with analogue design? 32:02 Python binding for spice: https://pypi.org/project/PySpice/ 33:02 Books by Behzad Razavi are recommended. Design repo: https://github.com/yrrapt/amsat_txrx_ic Shuttle application repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas here: https://www.linkedin.com/in/thomas-parry-60419468/

In this interview Sylvain talks about: 1:15? why he's excited about the shuttle 4:00? what is the design he's working on 8:00? expectation vs experience with the Open Source ASIC tools 8:57? a look at the final GDS files 14:20? differences between design for ASIC vs FPGA 16:38? tap cells 17:50? antenna rules Sylvain's previous streams on the Skywater 130nm PDK: https://www.youtube.com/watch?v=AT_Lc...? https://www.youtube.com/watch?v=gRYBd...? https://www.zerotoasic.com?

1:00? What made you excited about the shuttle? 2:22? The spectrometer design - radar signal processing 4:00? built in self test 4:18? in & output signals 6:00? design in Chisel 10:40? ASIC vs FPGA 11:30? showing the GDS 12:24? density of the design 13:30? contact details https://github.com/milovanovic/spectr...? https://www.zerotoasic.com/?

In this interview Arya Reais-Parsi talks about: 00:45? FPGA design is for a course 01:50? difference between other open FPGA fabrics 02:50? FPGAs as accelerators 04:27? their FPGA structure 06:30? how did they target ASIC? 09:27? GDS view of the FPGA structure 11:40? custom cells for FPGAs 14:40? making lab notes 16:00? how does actually taping something out change the feeling of the work? 17:10? how will this shuttle program changes things going forwards? 22:40? future of ASIC with more open tooling and access 24:30? toolchain for their FPGA: yosys & nextpnr Their group's application is here: https://github.com/ucb-cs250/caravel_...

00:36? Diego's background 01:30? choice of design and the new tools 02:50? digital vs analog process 09:05? op-amp specifications 12:35? schematic in xschem 13:40? open loop testbench 14:26? spice setup 15:37? simulation results 17:44? layout in magic 23:20? opamps placed in the user project wrapper of Caravel 27:20? testing the ASIC Diego on linked.in: https://www.linkedin.com/in/diego-joa...? Diego's ASIC submission: https://github.com/diegohernando/cara...? xschem: https://xschem.sourceforge.io/stefan/...?

00:00? introduction 01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...? 02:18? Questions from Niklas - time it takes, what's frustrating, fun? 05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel. 07:20? Question from Pepijn - what would you need to change to alter the PLL? 08:44? PLL overview 10:00? Lakshmi's design: Frequency divider 12:22? Phase frequency detector 13:32? Charge pump 14:37? Voltage controlled oscillator 16:40? combined designs with Diego Hernando 17:10? putting into the Caravel wrapper, adding space 18:56? Question from Brady - why design an integrated loop filter 20:01? Questions from Top - are there schematics? Process corners and ngspice convergence 22:05? Question from Steven: post silicon testing Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/? Repo: https://github.com/lakshmi-sathi/avsd...

https://github.com/antonblanchard/microwatt-caravel

00:12 Tim Edwards introduction 01:00 next steps after submission before files sent to Skywater 02:00 infrastructure - getting all the latest from everyone's repositories 03:05 size of the repos can be a problem 03:41 revolutionary part of this run is that everything is Open Source down to the GDS 04:51 Open Source PDK is what makes it possible to do this for eFabless 05:12 Why didn't we submit the source rather than the final GDS? 09:42 Got all the GDS2 files from the repos, what's the next step? 10:00 3 scripts, 1st applies a user id 13:04 2nd script does fill generation 16:14 3rd script does compositing 19:39 DRC count for Caravel 23:00 lots of people have helped make this happen 23:50 biggest project at eFabless 24:00 When do you think the files will get sent to Skywater? Open Source VLSI tools: http://opencircuitdesign.com/ eFabless: https://efabless.com/company

00:00 Intro 00:10 TT boards 00:51 TT04 closes on Friday 8th 01:09 ORConf https://orconf.org/ 01:21 Wuthering Bytes 01:53 FSiC videos released https://peertube.f-si.org/video-chann... 02:04 Hackaday Supercon 2023 02:19 YUG2 https://www.linkedin.com/posts/yosysh... 02:36 Silicon news - MPW3 and 2206 03:37 IHP workshop videos    • Introduction FMD-QNC project status a...   04:04 IHP cleanroom video footage

Interviews with:
Luca Alloatti Thomas Benz Jørgen Kragh Jakobsen Thomas Parry Rene Scholz Dan Fritchman Harald Pretl

Website: https://monster6502.com/ & visual 6502 http://www.visual6502.org/JSSim/index.html Eric's socials: https://twitter.com/TubeTimeUS & https://mastodon.social/@tubetime Other interviews: https://theamphour.com/609-open-circuits-with-eric-schlaepfer-and-windell-oskay/ & https://unnamedre.com/episode/58

https://arxiv.org/abs/2305.13243
00:00 Intro 01:21 Hardware security 02:54 How long have they been using AI to generate Verilog 05:26 Methodology 17:40 Humans in the loop 21:21 Some designs already taped out on TinyTapeout 3 26:49 How to contact

For TinyTapeout 3, Harald Pretl made an analog temperature sensor out of digital standard cells. In this interview he explains how he did it.

Jeremy Birch implemented a custom STA timing setup for Tiny Tapeout 3. In this interview we discuss his background, what we needed the check and the results.